Energy, Time, and Space Complexity Analysis of ALU Designs’ Spanning from 2000 to the Present

This paper looks into various metrics discussed in the designs of multiple different ALUs, such as the Clock gated ALU, the ALU utilizing Vedic Multiplier in its MAC unit, and the scalable DCT architecture ALU. The discussion of these designs and the subsequent metrics that will be analyzed will cover both time and space complexity, as well as the general desire for every new design to use less power as the design previous. The metrics that will be discussed throughout this literature will be power consumption, datapath/operand size, ITRS Technology node width, execution time, as well as clock rate. Looking into the trends of these metrics across time may give engineers insight into the future of ALU designs. Keywords— Clock rate, Energy Consumption, Power Dissipation, Data Bus Width, ALU (Arithmetic Logic Unit, CPU (Central Processing Unit), ITRS technology node, Execution Time.